Part Number Hot Search : 
GP1S44S1 DS1321 1192L 102M1 150FC ACP20015 SST405 CH8510
Product Description
Full Text Search
 

To Download PI3HDMI341ART Datasheet File

  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
 
 


  Datasheet File OCR Text:
  1 ps8883 01/05/07 advance information - company confidential PI3HDMI341ART 3:1 active hdmi 1.3 compatible switch with optimized equalization for enhanced signal integrity features ? supply voltage, v cc = 3.3v 5% ? each port is compatible w/ dvi, hdmi 1.1, hdmi 1.2 or hdmi 1.3 signals ? supports both ac-coupled and dc-coupled inputs ? support for 8-bit, 10-bit, and 12-bit deep color per channel ? high performance, up to 2.5 gbps per channel ? switching support for 3 side band signals (scl, sda and hpd) ? 5v tolerance on all side band signals ? scl, sda, and hpd pins are the only pins that can support hot insertion ? integrated 50-ohm ( 10% ) termination resistors at each high speed signal input ? confgurable output swing control (500mv, 750mv, 1000mv) ? confgurable pre-emphasis levels (0db, 1.5db, 3.5db, & 6.0db) ? confgurable de-emphasis (0db, -3.5db, -6.0db, -9.5db) ? optimized equalization single default setting will support all cable lengths ? esd protection = 8kv (typical) on high-speed data channels only ? propagation delay 2ns ? high impedance outputs when disabled ? packaging (pb-free & green): 80-contact lqfp (ff80) description pericom semiconductors PI3HDMI341ART 3:1 active switch circuit is targeted for high-resolution video networks that are based on dvi/hdmi standards and tmds signal processing. the PI3HDMI341ART is an active 3 tmds to 1 tmds receiver switch with hi-z outputs. the device receives differential signals from selected video components and drives the video display unit. it provides three controllable output swings that can be controlled through a single bit. the allowable output swings are 500mv, 750mv and 1000mv. this solution also provides a unique advanced pre-emphasis technique to increase rise and fall times which are reduced during transmission across long distances. each complete hdmi/dvi channel also has slower speed, side band signals, that are required to be switched. pericoms solution provides a complete solution by integrating the side band switch together with the high speed switch in a single solution. using equalization at the input of each of the high speed channels, pericom can successfully eliminate deterministic jitter caused by long cables from the source to the sink. the elimination of the deterministic jitter allows the user to use much longer cables (up to 25 meters). the maximum dvi/hdmi bandwidth of 2.5 gbps provides 12- bit deep color support, which is offered by hdmi revision 1.3. due to its active uni-directional feature, this switch is designed for usage only for the video receivers side. for consumer video networks, the device sits at the receivers side to switch between multiple video components, such as pc, dvd, stb, d-vhs, etc. the PI3HDMI341ART is the industrys frst active dvi/ hdmi switch compatible with hdmi 1.1, 1.2, and 1.3 which ensures transmitting high-bandwidth video streams from video components to the display unit. the PI3HDMI341ART also provides enhanced robust esd/eos protection of 8kv, which is required by many consumer video networks today. the optimized equalization provides the user a single optimal setting that can provide hdmi compliance for all cable lengths: 1meter to 20meters and color depths of 8bit/ch, or 12bit/ch. pericom also offers the abiility to fne tune the equalization settings in situations where cable length is known. for example, if 25meter cable length is required, pericom's solution can be adjusted to 16db eq to accept 25metere cable length.
2 ps8883 01/05/07 PI3HDMI341ART 3:1 active hdmi 1.3 compatible switch with optimized equalization for enhanced signal integrity advance information - company confidential pin confguration v cc hpd2 sda2 scl2 gnd gnd b21 a21 v cc a22 gnd b22 v cc gnd v cc hpd1 hpd_sink sda_sink scl_sin k gn d gn d z1 y1 v cc z2 y2 gn d z3 y3 v cc z4 y4 gn d s3 s2 s1 34 33 32 31 30 29 28 27 26 25 24 23 22 21 40 39 38 37 36 35 oc_s2 oc_s0 oc_s1 v cc gnd a14 b14 v cc a13 b13 gnd a12 b12 v cc a11 b11 gnd scl1 sda1 oc_s3 eq_s1 gnd a34 b34 a33 b33 gnd a32 b32 v cc a31 b31 gnd scl3 sda3 hpd3 v cc oe eq_s0 a23 b23 a24 b24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 67 68 69 70 71 72 73 74 75 76 77 78 79 80 61 62 63 64 65 66 v cc
3 ps8883 01/05/07 PI3HDMI341ART 3:1 active hdmi 1.3 compatible switch with optimized equalization for enhanced signal integrity advance information - company confidential pin description pin # pin name i/o description 6,9,12,15 a11, a12, a13, a14 i port 1 tmds positive inputs 68, 71, 74, 77 a21, a22, a23, a24 i port 2 tmds positive inputs 49, 52, 55, 58 a31, a32, a33, a34 i port 3 tmds positive inputs 5, 8, 11, 14 b11, b12, b13, b14 i port 1 tmds negative inputs 67, 70, 73, 76 b21, b22, b23, b24 i port 2 tmds negative inputs 48, 51, 54, 57 b31, b32, b33, b34 i port 3 tmds negative inputs 4, 10, 16 24, 30, 36, 37, 47, 53, 59, 65, 66, 72, 78 gnd ground 80 hpd1 o port 1 hpd output 62 hpd2 o port 2 hpd output 44 hpd3 o port 3 hpd output 40 hpd_sink i sink side hot plug detector input. high: 5-v power signal asserted from source to sink and edid is ready. low: no 5-v power signal asserted from source to sink, or edid is not ready. 42 oe i output enable, active low 3 scl1 i/o port 1 ddc clock 64 scl2 i/o port 2 ddc clock 46 scl3 i/o port 3 ddc clock 38 scl_sink i/o sink side ddc data 2 sda1 i/o port 1 ddc data 63 sda2 i/o port 2 ddc data 45 sda3 i/o port 3 ddc data 39 sda_sink i/o sink side ddc data 21,22,23 s1, s2, s3 i source input selector 7, 13, 17 27, 33, 43, 50, 56 61, 69, 75, 79 v cc 3.3v power supply 34, 31, 28, 25 y1, y2, y3, y4 o tmds positive outputs 35, 32, 29, 26 z1, z2, z3, z4 o tmds negative outputs 41, 60 eq_s0, eq_s1 i equalizer controls (1) 19, 18, 20, 1 oc_s0, oc_s1, oc_s2, oc_s3 i output buffer controls note: oc_s3 has an internal pull-up resistor. oc_s2 has an internal pull-down resistor. note: 1. eq_s0 has an internal pull-down and eq_s1 has an internal pull-up
4 ps8883 01/05/07 PI3HDMI341ART 3:1 active hdmi 1.3 compatible switch with optimized equalization for enhanced signal integrity advance information - company confidential switch block diagram ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ???????????? ? ?????? ??? ? ??? ? ???? ? ??? ? ???? ? ??? ? ???? ? ??? ? ???? ? ???? ? ???? ? ???? ? ? ??? ? ??? ? ??? ? ??? ? ??? ? ??? ? ??? ? ??? ? ??? ? ??? ? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ? ??? ? ??? ? ? ?? ??? ? ?? ??? ? ?? ??? ? ?? ?? ? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ???????? ???????? ??? ? ??? ? ??? ? ??? ? ??? ? ??? ? ???????? ????? ????? ????? ???? ? ???? ? ???? ?
5 ps8883 01/05/07 PI3HDMI341ART 3:1 active hdmi 1.3 compatible switch with optimized equalization for enhanced signal integrity advance information - company confidential truth table control pins i/o selected hot plug detect status s1 s2 s3 y/z scl_sink sda_sink hpd1 hpd2 hpd3 h x x a1/b1 scl1 sda1 hpd_sink l l l h x a2/b2 scl2 sda2 l hpd_sink l l l h a3/b3 scl3 sda3 l l hpd_sink l l l none (hi-z) none (hi-z) l l l oc setting value logic table input control pins setting value oc_s3 oc_s2 oc_s1 oc_s0 v swing (mv) v os (v) pre-emphasis/de-emphasis (db) 0 0 0 0 500 3.06 none 0 0 0 1 750 2.95 none 0 0 1 0 1000 2.84 none 0 0 1 1 500 3.02 none 0 1 0 0 500 3.06 0 0 1 0 1 500 3.05 1.5 0 1 1 0 500 2.97 3.5 0 1 1 1 500 2.9 6 1 0 0 0 500 3.08 0 1 0 0 1 340 3.08 -3.5 1 0 1 0 270 3.08 -6 1 0 1 1 160 3.08 -9.5 1 1 0 0 1000 2.85 0 1 1 0 1 830 2.85 -3.5 1 1 1 0 500 2.85 -6 1 1 1 1 330 2.85 -9.5 eq setting value logic table eq_s1 eq_s0 setting value 0 0 3db on all high speed inputs 0 1 8db on all high speed inputs 1 0 optimized equalization enabled on all high speed inputs (default value if both eq_s0 and eq_s1 are left foating) 1 1 16db on all high speed inputs
6 ps8883 01/05/07 PI3HDMI341ART 3:1 active hdmi 1.3 compatible switch with optimized equalization for enhanced signal integrity advance information - company confidential storage temperature .................................................... C65c to +150c supply voltage to ground potential ................................ C0.5v to +4.0v dc input voltage ............................................................... C0.5v to v cc dc output current ............................................................... ........ 120ma power dissipation ............................................................... ............ 1.0w note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to ab - solute maximum rating conditions for extended periods may affect reliability. maximum ratings (above which useful life may be impaired. for user guidelines, not tested.) recommended operating conditions symbol parameter min. typ. max. units v cc supply voltage 3.135 3.3 3.465 v t a operating free-air temperature 0 70 c tmds differential pins (a/b) v id receiver peak-to-peak differential input voltage 150 1560 mvp-p v ic input common mode voltage 2 v cc + 0.01 v v cc tmds output termination voltage 3.135 3.3 3.465 v r t termination resistance 45 50 55 ohm signaling rate 0 2.5 gbps control pins (oc_sx, eq_sx, s, oe) v ih lvttl high-level input voltage 2 v cc v v il lvttl low-level input voltage gnd 0.8 ddc pins (scl, scl_sink, sda, sda_sink) v i(ddc) input voltage gnd 5.5 v status pins (hpd_sink) v ih lvttl high-level input voltage 2 5.3 v v il lvttl low-level input voltage gnd 0.8
7 ps8883 01/05/07 PI3HDMI341ART 3:1 active hdmi 1.3 compatible switch with optimized equalization for enhanced signal integrity advance information - company confidential item hdmi 1.3 spec pericom product spec operating conditions termination supply voltage, v cc 3.3v 5% 3.30 5% terminal resistance 50-ohm 10% 45 to 55-ohm source dc characteristics at tp1 single-ended high level output voltage, vh v cc 10mv v cc 10mv single-ended low level output voltage, vl ( v cc - 600mv) vl ( v cc - 400mv) ( v cc - 600mv) vl ( v cc - 400mv) single-ended output swing voltage, vswing 400mv vswing 600mv 400mv vswing 600mv single-ended standby (off) output voltage, voff v cc 10mv v cc 10mv transmitter ac characteristics at tp1 risetime/falltime (20%-80%) 75ps risetime/falltime 0.4 tbit (75ps tr/tf 242ps) @ 1.65 gbps 240ps intra-pair skew at transmitter connector, max 0.15 tbit (90.9ps @ 1.65 gbps) 60ps max inter-pair skew at transmitter connector, max 0.2 tpixel (1.2ns @ 1.65 gbps) 100ps max clock jitter, max 0.25 tbit (151.5ps @ 1.65 gbps) 82ps max sink operating dc characteristics at tp2 input differential voltage level, vdiff 150 vdiff 1200mv 150mv v diff 1200mv input common mode voltage level, v icm ( v cc - 300mv) vicm ( v cc - 37.5mv) or v cc 10% ( v cc - 300mv) vicm ( v cc - 37.5mv) or v cc 10% sink dc characteristics when source disabled or disconnected at tp2 differential voltage level v cc 10mv v cc 10mv tmds compliance test results
8 ps8883 01/05/07 PI3HDMI341ART 3:1 active hdmi 1.3 compatible switch with optimized equalization for enhanced signal integrity advance information - company confidential electrical characteristics (over recommended operating conditions unless otherwise noted) symbol parameter test conditions min. typ. (1) max. units i cc supply current v ih = v cc , v il = v cc - 0.4v, r t = 50-ohm, v cc = 3.3v am/bm = 1.65 gbps hdmi data pattern, m = 2, 3, 4 a1/b1 = 165 mhz clock 190 230 ma p d power dissipation 394 657 mw tmds differential pins (a/b; y/z) v oh single-ended high-level output voltage v cc = 3.3v, r t = 50-ohm pre-emphasis/de-emphasis = 0db v cc - 10 v cc + 10 mv v ol single-ended low-level output voltage v cc - 600 v cc - 400 v swing single-ended output swing voltage 400 600 v od(o) overshoot of output differential volt - age 6% 15% 2x v swing v od(u) undershoot of output differential volt - age 12% 25% v oc(ss) change in steady-state common-mode output voltage between logic states 0.5 5 mv |i (os) | short circuit output current 12 ma v ode(ss) steady state output differential voltage oc_s0 = v cc , am/bm = 250 mbps hdmi data pattern, m = 2, 3, 4 a1/b1 = 25 mhz clock 560 840 mvp-p v ode(pp) peak-to-peak output differential voltage 800 1200 v i(open) single-ended input voltage under high impedance input or open input i i = 10a v cc - 10 v cc + 10 mv r int input termination resistance v in = 2.9v 45 50 55 ohm ddc i/o pins (scl, scl_sink, sda, sda_sink) |i lkg | input leakage current v i = 0.1v cc to 0.9v cc to isolated ddc ports 0.1 2 a c io input/output capacitance v i = 0v 7.5 pf r on switch resistance i o = 3ma, v o = 0.4v 25 50 ohm v pass switch output voltage v i = 3.3v, i i = 100a 1.5 (2) 2.0 2.5 (3) v status pins (hpd) v oh(ttl) ttl high-level output voltage i oh = -8ma 2.4 v v ol(ttl) ttl low-level output voltage i oh = 8ma 0.4 v (table continued)
9 ps8883 01/05/07 PI3HDMI341ART 3:1 active hdmi 1.3 compatible switch with optimized equalization for enhanced signal integrity advance information - company confidential symbol parameter test conditions min. typ. (1) max. units control pins (oc_sx, eq_sx, s, oe) |i ih | high-level digital input current v ih = 2.0v or v cc 0.1 2 a |i il | low-level digital input current v il = gnd or 0.8v 0.1 2 status pins (hpd_sink) |i ih | high-level digital input current v ih = 5.3v 23 100 a v ih = 2.0v or v cc 0.1 2 |i il | low-level digital input current v il = gnd or 0.8v 0.1 2 electrical characteristics (continued) notes: 1. all typical values are at 25 c and with a 3.3v supply. 2. the value is tested in full temperature range at 3.0v. 3. the value is tested in full temperature range at 3.6v.
1 0 ps8883 01/05/07 PI3HDMI341ART 3:1 active hdmi 1.3 compatible switch with optimized equalization for enhanced signal integrity advance information - company confidential switching characteristics (over recommended operating conditions unless otherwise noted) symbol parameter test conditions min. typ. (1) max. units tmds differential pins (y/z) tpd propagation delay v cc = 3.3v, r t = 50-ohm, pre-emphasis/de-emphasis = 0db 2000 ps t r differential output signal rise time (20% - 80%) 75 240 t f differential output signal fall time (20% - 80%) 75 240 t sk(p) pulse skew 7 50 t sk(d) intra-pair differential skew 23 50 t sk(o) inter-pair differential skew (2) 100 t jit(pp) peak-to-peak output jitter from y/z(1) residual jitter pre-emphasis/de-emphasis = 0db, am/bm = 1.65 gbps hdmi data pat - tern, m = 2 ,3, 4 a1/b1 = 165 mhz clock 15 30 t jit(pp) peak-to-peak output jitter from y/z(2:4) residual jitter 18 50 t de de-emphasis duration de-emphasis = -3.5db, am/bm = 250 mbps hdmi data pattern, m = 2, 3, 4 a1/b1 = 25 mhz clock 240 t sx select to switch output 6 10 ns t en enable time 6 10 t dis disable time 6 10 ddc i/o pins (scl, scl_sink, sda, sda_sink) t pd(ddc) propagation delay from scln to scl_sink or sdan to sda_sink or sda_sink to sdan c l = 10pf 0.4 2.5 ns control and status pins (oc_sx, eq_sx, s, hpd_sink, hpd) t pd(hpd) propagation delay (from hpd_sink to the active port of hpd) c l = 10pf 2 6.0 ns t sx(hpd) switch time (from port select to the lat - est valid status of hpd) 3 6.5 notes: 1. all typical values are at 25 c and with a 3.3v supply. 2. t sk(o) is the magnitude of the difference in propagation delay times between any specifed terminals of channel 2 to 4 of a device when inputs are tied together. application information supply voltage all v cc pins are recommended to have a 0.01uf capacitor tied from v cc to gnd to flter supply noise tmds inputs standard tmds terminations have already been integrated into pericoms PI3HDMI341ART device. therefore, external termina - tions are not required. any unused port must be left foating and not tied to gnd.
1 1 ps8883 01/05/07 PI3HDMI341ART 3:1 active hdmi 1.3 compatible switch with optimized equalization for enhanced signal integrity advance information - company confidential pericom semiconductor corporation ? 1-800-435-2336 ? www.pericom.com ordering information ordering code package code package description PI3HDMI341ARTffe ff 80-pin, pb-free & green lqfp notes: ? thermal characteristics can be found on the company web site at www .pericom.com/packaging/ ? e = pb-free and green ? adding an x suffx = tape/reel 1 description: 80-pin, low profle quad flat package (lqfp) package code: ff80 document control #: pd-2064 revision: - notes: 1) all dimensions are in millimeters, angles in degrees 2) ref jedec: ms-026/bdd 3) package outline exclusive of mold fash and metal burr date: 07/27/06


▲Up To Search▲   

 
Price & Availability of PI3HDMI341ART

All Rights Reserved © IC-ON-LINE 2003 - 2022  

[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]


 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X